library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity execute is
    port(
    RegWriteInE, MemToRegInE, MemWriteInE, JumpInE, BranchInE, AluSrcE, RegDstE:
        in std_logic;
    AluControlE:
        in std_logic_vector(2 downto 0);
    RtE, RdE:
        in std_logic_vector(4 downto 0);
    RD1E, RD2E, PCPlus4E, SignImmE:
        in std_logic_vector(31 downto 0);

    RegWriteOutE, MemToRegOutE, MemWriteOutE, JumpOutE, BranchOutE, ZeroE:
        out std_logic;
    WriteRegE:
        out std_logic_vector(4 downto 0);
    AluResE, WriteDataE, PCBranchE: 
        out std_logic_vector(31 downto 0)
    );
end execute;

architecture behav of execute is
    component alu
        port(
        a, b: in std_logic_vector(31 downto 0);
        alucontrol: in std_logic_vector(2 downto 0);
        result: out std_logic_vector(31 downto 0);
        zero: out std_logic
        );
    end component;

    component mux2
        generic(n: integer);
        port(
        d0, d1: in std_logic_vector(n downto 0);
        s: in std_logic;
        y: out std_logic_vector(n downto 0)
        );
    end component;

    component sl2
        port(
        a: in std_logic_vector(31 downto 0);
        y: out std_logic_vector(31 downto 0)
        );
    end component;

    component adder
        port(
        a, b: in std_logic_vector(31 downto 0);
        s: out std_logic_vector(31 downto 0)
        );
    end component;

    signal SrcBE, SL2_Out: std_logic_vector(31 downto 0);
begin
    EX_alu: alu
        port map(RD1E, SrcBE, AluControlE, AluResE, ZeroE);
    EX_mux2_5: mux2
        generic map(4)
        port map(RtE, RdE, RegDstE, WriteRegE);
    EX_mux2_32: mux2
        generic map(31)
        port map(RD2E, SignImmE, AluSrcE, SrcBE);
    EX_sl2: sl2 
        port map(SignImmE, SL2_Out);
    EX_adder: adder
        port map(SL2_Out, PCPlus4E, PCBranchE);

    RegWriteOutE <= RegWriteInE;
    MemToRegOutE <= MemToRegInE;
    MemWriteOutE <= MemWriteInE;
    JumpOutE <= JumpInE;
    BranchOutE <= BranchInE;
    WriteDataE <= RD2E;
end behav;
